Providing some degree of strain to the channel of a semiconductor device such an n-type field effect transistor (NFET) or a p-type field effect transistor (PFET) to improve device performance is known in the art. High performance semiconductor devices employ such strain to provide higher carrier mobility, lower transistor on-resistance, increased drive current (on-current), etc.
One method of providing strain to the channel of a semiconductor device is to embed a lattice-mismatched and epitaxially aligned semiconductor material adjacent to the channel of the field effect transistor. Exemplary latticed mismatched materials that may be embedded into a silicon substrate to provide a strain to a channel comprising silicon include a silicon-germanium alloy, a silicon-carbon alloy, a silicon-germanium-carbon alloy, etc. The placement of the embedded lattice-mismatched and epitaxially aligned semiconductor material in proximity to the channel induces a compressive strain or a tensile strain in the channel. Typically, a compressive strain is employed to enhance the charge carrier mobility of a PFET, and a tensile strain is employed to enhance the charge carrier mobility of an NFET. The greater the strain, the greater the enhancement of the charge carrier mobility and the enhancement of performance, as long as epitaxial alignment between the embedded semiconductor material and the semiconductor material of the substrate is maintained.
Some of the most destructive processing steps that often serve to reduce the stain generated by embedded semiconductor material portions are ion implantation steps that are employed to dope portions of the semiconductor substrate. Such ion implantation steps include deep source/drain ion implantation steps (or “source/drain ion implantation” steps), source/drain extension ion implantation steps (or “extension ion implantation” steps), and halo ion implantation steps. Such ion implantation steps introduce crystalline defects into the embedded semiconductor material portions, and thereby induce reduction of the magnitude of the strain applied to the channel of the semiconductor device. Such reduction in the magnitude of the strain reduces the degree of performance enhancement in the semiconductor devices.